1. Field of the Invention
The present invention relates to an apparatus and method for filtering special cycles of a microprocessor from appearing on the host bus to prevent improper operations.
2. Description of the Related Art
Microprocessor-based computer systems have been increasing in performance at a tremendous rate. Much of this increase has been based on the improvements in the microprocessor itself. For example, clock speeds are reaching those previously used only by main frame computers. The P5 or Pentium microprocessor, manufactured by Intel Corporation (Intel), is a next generation microprocessor which has very high performance including superscalar architecture and integrated and separate code and data internal caches. The internal data cache is a write-back cache. The P5 uses a full 64-bit data path and provides significant performance improvements over the 32-bit data path used by prior microprocessors. The P5 is designed to be fully software-compatible with the 80386 and the i486 microprocessors, also manufactured by Intel, even though the 80386 and i486 microprocessors operate on a 32-bit data path and typically at slower clock rates. The Host bus for systems based on the 80386 or i486 microprocessors also use a 32-bit data path and the clock speed of the microprocessor, such as 25 or 33 MHz.
It is considered desirable to upgrade existing computer systems based on the 80386 or i486 microprocessors to utilize the advances provided by the P5 processor, without significantly affecting the remaining portions of the computer system. For example, a computer system may include a processor portion, a system board portion and an input/output (I/O) portion, where the processor and system portions are typically separated by a host bus. The I/O portion is typically centered around an I/O or expansion bus, such as the Industry Standard Architecture (ISA) or the Extended ISA (EISA) bus. A bus controller, such as an EISA bus controller (EBC), is coupled between the host and I/O buses. Since devices coupled to the host bus and residing on the system board are compatible with the host bus, the data width, clock speed and other specifications must remain mostly unchanged. Thus, it is desirable to upgrade the processor portion while leaving the system and I/O portions substantially unchanged.
The most obvious approach would be to use a P5 as the processor in a 386/486 microprocessor host bus system, where the host bus is isolated from the processor bus with cycle conversion logic. The cycle conversion logic would simply convert each 64-bit cycle to two 32-bit cycles. It has been discovered, however, that this simple solution is not adequate and causes erroneous operation. To illustrate this problem, it is first necessary to discuss special cycles executed by the microprocessors.
The 80386 and i486 microprocessors include four special cycles which are decoded using several control and byte enable signals to indicate which one of the four cycles is being executed. The four special cycles include a shutdown cycle, which is executed as a result of either an exception occurring while the microprocessor was attempting to call a double fault handler or when an internal parity error is detected. The shutdown cycle can also be initiated through software. Microprocessor utility logic, otherwise referred to as the CUC, is typically provided to detect the shutdown special cycle on the host bus and to respond by resetting the microprocessor. The bus controller also interprets the shutdown cycle and also asserts a signal to reset the microprocessor. A second special cycle, referred to as flush, is executed when a cache invalidate instruction is executed by the microprocessor. A third special cycle, referred to as halt, occurs after the microprocessor performs a HALT instruction. The fourth and final special cycle, referred to as write-back, occurs after the microprocessor executes a write-back invalidate instruction, to cause any write-back caches to flush. The M/IO* (memory/I/O), D/C* (data/code) and W/R* (write/read) signals, when asserted low, low and high respectively, indicate a special cycle is occurring. Four byte enable bits BE3*-BE0* indicate which of the four special cycles is occurring, where only one of the byte enable bits is asserted at a time during special cycles. An asterisk at the end of a signal name indicates negative logic, the signal being asserted when low. A shutdown special cycle is indicated as BE0* being 0, a FLUSH special cycle is indicated as BE1* being 0, a HALT special cycle is indicated as BE2* being 0 and a WRITE-BACK special cycle is indicated when BE3* is 0.
The P5 microprocessor uses four additional byte enable bits because of its 64 bit data path for a total of eight, namely BE7*-BE0*. The P5 supports all four of the special cycles described above plus two more. The first new special cycle is called a flush acknowledge, which is executed after the P5 writes back all of its dirty lines and flushes its internal data cache as a result of its input pin FLUSH* being asserted low, to indicate completion of the flush request. The P5 supports a second new special cycle, referred to as a branch trace message, which occurs if a tracing enable bit is set and if a branch instruction is executed and the branch is taken. The flush acknowledge and branch trace message special cycles are indicated by the same control signals, but the BE4* bit is asserted low for the flush acknowledge and the BE5* bit is asserted low for the branch trace message special cycle, respectively.
Cycle conversion logic coupled between the P5 microprocessor and the host bus converts a 64-bit cycle into two 32-bit cycles, which means that the upper BE7*-BE4* byte enable bits are remapped to the lower BE3*-BE0* byte enable bits during the second of the two 32-bit cycles executed on the host bus. This would cause erroneous operation, since the CUC logic would decode a flush acknowledge cycle as a shutdown cycle and would decode a branch trace message special cycle as a flush special cycle. Similarly, the bus controller also misinterprets the flush acknowledge and causes erroneous operation. Indeed, both the CUC and the bus controller would issue reset signals if the flush acknowledge special cycle were executed on the host bus, as that is the proper operation upon receipt of a shutdown indication.
It is therefore desirable to be able to use a P5 processor including the two new special cycles in cooperation with the host and I/O buses of 80386 or i486 microprocessor based systems with proper operation for all special cycles provided by the P5 processor.